High-frequency amplifier

ABSTRACT

Between resistors  13, 14  and an NPN bipolar transistor  12  are interposed PNP bipolar transistors  21, 22  forming a current mirror  20  that uses a collector current of the NPN bipolar transistor  12  as a reference current, and determines a collector current of an NPN bipolar transistor  11 . This makes possible to design a size ratio A of the PNP bipolar transistors  21, 22  so as to approximate a voltage drop ΔVb to a value close to zero, and to suppress the voltage drop ΔVb of the base voltage Vb accordingly to achieve a high power output and high efficiency when a high frequency input signal Pin increases and generates a base rectified current.

This application is the national phase under 35 U.S.C. § 371 of PCTInternational Application No. PCT/JP00/07085 which has an Internationalfiling date of Oct. 12, 2000, which designated the United States ofAmerica.

TECHNICAL FIELD

The present invention relates to a high frequency amplifying device foruse in a satellite communication, ground microwave communication, mobilecommunication, and the like.

BACKGROUND ART

Generally, a high frequency amplifier using an NPN bipolar transistor ofthe BJT, HBT, or the like takes on a constant voltage biasing circuitthat applies a constant voltage to the base in order to achieve a highpower output and high efficiency. When a constant bias current isapplied to the base, and when power of a high frequency input signalincreases and generates a rectified current, the base voltage drops inorder to maintain the constant current. Accordingly, when the power ofinput signal increases, since the amplifier operation rapidly approachesto the B-class, the saturation power decreases, and the high poweroutput and high efficiency cannot be achieved. When a constant biasvoltage is applied to the base, on the other hand, since the basevoltage will not drop, the biasing class does not change, and a greatersaturation power output and higher efficiency can be attained incomparison to the case of the constant current biasing. Therefore, aconstant voltage biasing circuit that does not lower the base voltage,becomes necessary even when there is an increase of the base currentwith an increase of the power of input signal.

FIG. 1 is a circuit diagram illustrating a high frequency amplifyingdevice, in that a base current compensating current mirror circuit isused for the constant voltage biasing circuit, which is presented, forexample, in “Introduction To Functional Circuit Design of Analog ICs, ICDesigning Method Using Circuit Simulator SPICE” (written by HidehikoAoki, issued by the CQ publisher, Sep. 20, 1992, page 74).

In the drawing, reference numeral 1 signifies a high frequency amplifierusing an NPN bipolar transistor such as the BJT, HBT, or the like, asthe amplifying element, and 2 signifies a constant voltage biasingcircuit that supplies a base bias voltage to the high frequencyamplifier 1.

In the high frequency amplifier 1, reference numeral 3 signifies an NPNbipolar transistor such as the BJT, HBT, or the like, 4 signifies theground connected to the emitter terminal of the NPN bipolar transistor3, 5 signifies a high frequency signal in,put terminal, 6 signifies ahigh frequency signal output terminal, 7 signifies a base bias terminal,8 signifies a collector bias terminal.

In the constant voltage biasing circuit 2, reference numeral 11signifies an NPN bipolar transistor such as the BJT, HBT, or the like,which configures a current mirror circuit together with the NPN bipolartransistor 3 of the high frequency amplifier 1, whose base terminal isconnected to the base bias terminal 7, whose emitter terminal isconnected to the ground 4. Reference numeral 12 signifies an NPN bipolartransistor such as the BJT, HBT, or the like, for a base currentcompensation, whose base terminal is connected to the collector terminalof the NPN bipolar transistor 11, whose emitter terminal is connected tothe base terminal of the NPN bipolar transistor 11. Reference numeral 13signifies a resistor connected between the collector terminal of the NPNbipolar transistor 12 and a power supply/voltage setting terminal 15,and 14 signifies a resistor connected between the base terminal of theNPN bipolar transistor 12 and the power supply/voltage setting terminal15.

Next, the operation will be described.

A high frequency signal Pin is input to the high frequency amplifier 1through the high frequency signal input terminal 5, and is output fromthe high frequency signal output terminal 6, after being amplified bythe high frequency amplifier 1. A base voltage Vb and a base currentIbrf to the high frequency amplifier 1 are supplied from the constantvoltage biasing circuit 2, and a collector current Icrf and a collectorvoltage Vc to the high frequency amplifier 1 are supplied from thecollector bias terminal 8.

In the constant voltage biasing circuit 2, the base voltage Vb and thebase current Ibrf are determined as follows. Here, it is supposed that asize of the NPN bipolar transistor 11 that forms the current mirrortogether with the high frequency amplifier, 1 is 1, a size of the NPNbipolar transistor 3 of the high frequency amplifier 1 is N, and a sizeof the NPN bipolar transistor 12 for the base current compensation is M.Also, it is supposed that these three NPN bipolar transistors 3, 11, 12have the same structure and the same current amplification factor β.Further, the contact voltage Vref, the currents Iref, Icdc1, Ibdc1,Icdc2, Iedc2, Ibdc2, Ibrf, Icrf, and the resistor Rref are defined asshown in FIG. 1.

When a power supply voltage Vpc is supplied from the powersupply/voltage setting terminal 15 of the constant voltage biasingcircuit 2, the reference current Iref of the current mirror is given bythe following expression.

Iref=(Vpc−2*Vb)/Rref

With regard to this reference current Iref, the collector current Icrfof the NPN bipolar transistor 3 of the high frequency amplifier 1 isgiven as follows.${Icrf} = {\frac{N}{1 + \frac{1 + N}{\beta \cdot ( {1 + \beta} )}}{Iref}}$

Where the base bias voltage Vb of the NPN bipolar transistor 3 of thehigh frequency amplifier 1 is set as follows.

Vb=(Vpc−Iref*Rref)/2

The base current Ibrf flowing in this case becomes as follows.

Ibrf=Icrf/β

In this manner, the constant voltage biasing circuit 2 supplies the basevoltage Vb and the base current Ib as the output thereof.

Since the conventional high frequency amplifying device is configured asabove, when the high frequency input signal Pin increases and generatesa base rectified current ΔIb, the base voltage Vb lowers by a voltagedrop of ΔVb. Therefore, when the high frequency input signal Pinincreases, the biasing class of the high frequency amplifier 1approaches to the B-class, and the saturation output power andefficiency are decreased, which is a problem. Hereunder, the operationto cause the voltage drop ΔVb will be explained.

In the conventional technique, a case will be examined, in which theinput power of the high frequency amplifier 1 increases and generatesthe base rectified current of ΔIb, and consequently the constant voltagebiasing circuit 2 increases the output of the base current Ibrf by ΔIb.When the base current Ibrf increases by ΔIb, assuming that the emittercurrent Iedc2 of the NPN bipolar transistor 12 for the base currentcompensation increases by ΔIedc2, and the base current Ibdc1 of the NPNbipolar transistor 11 that forms the current mirror decreases by ΔIbdc1,there is the following relation on the variations of these currents.

ΔIb=ΔIedc2+ΔIbdc1

Next, a variation ΔIcdc1 of the base current Icdc1 of the NPN bipolartransistor 11 that forms the current mirror is given as follows.

ΔIcdc1=−β*ΔIbdc1

Here, assuming that the reference current Iref is almost constant, avariation ΔIbdc2 of the base current Ibdc2 of the NPN bipolar transistor12 for the base current compensation is given as follows.

ΔIbdc2=−ΔIcdc1=β*ΔIbdc1

Therefore, the variation ΔIedc2 of the emitter current Iedc2 of the NPNbipolar transistor 12 for the base current compensation is given asfollows.

ΔIedc2=(1+β)*ΔIbdc2=β*(1+β)*ΔIbdc1

Therefore,

ΔIb=ΔIedc2+ΔIbdc1=ΔIbdc1*{1+β*(1+β)}=ΔIbdc1*(1+β+β²)

Therefore, ΔIbdc1 is given as follows.${\Delta \quad {Ibdc1}} = \frac{\Delta \quad {Ib}}{1 + \beta + \beta^{2}}$

The voltage drop at this moment of the NPN bipolar transistor 11 thatforms the current mirror, namely the voltage drop ΔVb of the outputvoltage Vb is given as follows.${\Delta \quad {Vb}} = {{\frac{q}{nkT}{\ln( {1 - \frac{\Delta \quad {Ib}}{{Is} \cdot ( {1 + \beta + \beta^{2}} ) \cdot e^{\frac{qVb}{nkT}}}} )}} < 0}$

Where n is the compensation coefficient, k is the Boltzmann's constant,T is the absolute temperature, q the electric charge, and Is thesaturation current.

Accordingly, in the high frequency amplifier of the conventionaltechnique, when the high frequency input signal Pin increases andgenerates the base rectified current ΔIb, the base voltage Vb generatesthe voltage drop of ΔVb; and as a result, the biasing class of the highfrequency amplifier 1 approaches the B-class when the high frequencyinput signal Pin increases, which leads to a problem that the saturationoutput power and the efficiency are decreased.

The present invention has been made in order to solve the foregoingproblem, and an object of the present invention is to achieve a highfrequency amplifier that maintains a high efficiency, even if the highfrequency input signal increases and generates the base rectifiedcurrent.

Disclosure of Invention

The high frequency amplifying device according to this invention isprovided, between a first and second resistors and a third NPN bipolartransistor, with a first and second PNP bipolar transistors forming acurrent mirror that uses a collector current of the third NPN bipolartransistor as a reference current, and determines a collector current ofa second NPN bipolar transistor.

With this configuration, designing a size ratio of the first and secondPNP bipolar transistors forming the current mirror so as to approximatea voltage drop to just zero, or a value infinitely close to zero willsuppress the voltage drop of the base voltage, when the high frequencyinput signal increases and generates a base rectified current, whicheffects a high power output and high efficiency.

Further, varying the size ratio of the first and second PNP bipolartransistors forming the current mirror will adjust, i.e., increase,regularize, or decrease the base voltage, when the high frequency in putsignal increases and generates the base rectified current, thuseffecting a function to adjust the base voltage.

The high frequency amplifying device according to this invention isprovided, between a first and second resistors and a third NPN bipolartransistor, with a first and second PMOS transistors forming a currentmirror that uses a collector current of the third NPN bipolar transistoras a reference current, and determines a collector current of a secondNPN bipolar transistor.

With this configuration, designing a size ratio of the first and secondPMOS transistors forming the current mirror so as to approximate avoltage drop to just zero, or a value infinitely close to zero willsuppress the voltage drop of the base voltage, when the high frequencyinput signal increases and generates a bases rectified current, whicheffects a high power output and high efficiency.

Further, varying the size ratio of the first and second PMOS transistorsforming the current mirror will adjust, i.e., increase, regularize, ordecrease the base voltage, when the high frequency input signalincreases and generates the base rectified current, thus effecting afunction to adjust the base voltage.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram illustrating a conventional high frequencyamplifying device;

FIG. 2 is a circuit diagram illustrating a high frequency amplifyingdevice according to an embodiment 1 of the present invention; and

FIG. 3 is a circuit diagram illustrating a high frequency amplifyingdevice according to an embodiment 2 of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

In order to explain the present invention more in detail, the best modefor carrying out the present invention will be described with referenceto the accompanying drawings.

EMBODIMENT 1

FIG. 2 is a circuit diagram illustrating a high frequency amplifyingdevice according to an embodiment 1 of the present invention, and in thefigure, reference numeral 1 signifies a high frequency amplifier usingan NPN bipolar transistor such as the BJT, HBT, or the like, as anamplifying element, and 2 signifies a constant voltage biasing circuitthat supplies a base bias voltage to the high frequency amplifier 1.

In the high frequency amplifier 1, reference numeral 3 signifies an NPNbipolar transistor (a first NPN bipolar transistor) such as the BJT,HBT, or the like, 4 a ground connected to the emitter terminal of theNPN bipolar transistor 3, 5 a high frequency signal input terminal, 6 ahigh frequency signal output terminal, 7 a base bias terminal, 8 acollector bias terminal.

In the constant voltage biasing circuit 2, reference numeral 11signifies an NPN bipolar transistor (a second NPN bipolar transistor)such as the BJT, HBT, or the like, which configures a current mirrorcircuit together with the NPN bipolar transistor 3 of the high frequencyamplifier 1, whose base terminal is connected to the base bias terminal7, whose emitter terminal is connected to the ground 4. Referencenumeral 12 signifies an NPN bipolar transistor (a third NPN bipolartransistor) such as the BJT, HBT, or the like, for a base currentcompensation, whose base terminal is connected to a collector terminalof the NPN bipolar transistor 11, whose emitter terminal is connected toa base terminal of the NPN bipolar transistor 11.

Further, reference numeral 20 signifies a current mirror that uses acollector current of the NPN bipolar transistor 12 as a referencecurrent, and determines the collector current of the NPN bipolartransistor 11, 21, 22 signify PNP bipolar transistors (first and secondPNP bipolar transistors) such as the BJT, HBT, or the like, whichconstitute the current mirror. In the current mirror, the bases of thePNP bipolar transistors 21, 22 are connected each other, the base andcollector terminals of the PNP bipolar transistor 21 are commonlyconnected to the collector terminal of the NPN bipolar transistor 12,and the collector terminal of the PNP bipolar transistor 22 is connectedto the base terminal of the NPN bipolar transistor 12.

Reference numeral 13 signifies a resistor (a first resistor) connectedbetween the emitter terminal of the PNP bipolar transistor 21 and apower supply/voltage setting terminal 15, 14 a resistor (a secondresistor) connected between the emitter terminal of the PNP bipolartransistor 22 and the power supply/voltage setting terminal 15, 41 aresistor connected between the collector terminal of the PNP bipolartransistor 22 and the power supply/voltage setting terminal 15, and 42 astart-up circuit composed of the resistor 41.

Next, the operation will be described.

A high frequency signal Pin is inputted to the high frequency amplifier1 through the high frequency signal input terminal 5, and is output fromthe high frequency signal output terminal 6 after being amplified by thehigh frequency amplifier 1. A base voltage Vb and a base current Ibrfare supplied from the constant voltage biasing circuit 2, and acollector current Icrf and a collector voltage Vc are supplied from thecollector bias terminal 8.

In the constant voltage biasing circuit 2, the base voltage Vb and thebase current Ibrf are determined as follows. Herein, it is supposed thatthe size of the NPN bipolar transistor 11 that forms the current mirrortogether with NPN bipolar transistor 3 of the high frequency amplifier 1is 1, the size of the NPN bipolar transistor 3 of the high frequencyamplifier 1 is N, and the size of the NPN bipolar transistor 12 for thebase current compensation is M. Also, it is supposed that these threeNPN bipolar transistors 3, 11, 12 have the same structure and the samecurrent amplification factor β. Further, it is supposed that a sizeratio of the PNP bipolar transistors 21, 22 that form the current mirror20 is 1:A as shown in FIG. 2, and the current amplifying factor is β2.Further, the contact voltage Vref, the currents Iref, Icdc1, Ibdc1,Icdc2, Iedc2, Ibdc2, Ibrf, Icrf, and the resistor Rref are defined asshown in FIG. 2.

When a power supply voltage Vpc is supplied from the powersupply/voltage setting terminal 15 of the constant voltage biasingcircuit 2, the reference current Iref of the current mirror composed ofthe NPN bipolar transistors 3, 11 is given by the following expression,provided that the voltage across the base and emitter of the PNP bipolartransistor 22 is Vbpnp,

Iref=(Vpc−2*Vb−Vbpnp)/Rref

With regard to this reference current Iref, the collector current Icrfof the NPN bipolar transistor 3 of the high frequency amplifier 1 isgiven as follows.${Icrf} = {\frac{N}{1 + \frac{1 + N}{\beta \cdot ( {1 + \beta} )}}{Iref}}$

Where the base bias voltage Vb of the NPN bipolar transistor 3 of thehigh frequency amplifier 1 is set as follows.

Vb=(Vpc−Iref*Rref−Vbpnp)/2

The base current Ibrf flowing in this case becomes as follows.

Ibrf=Icrf/β

In this manner, the constant voltage biasing circuit 2 supplies the basevoltage Vb and the base current Ib as the output thereof. Incidentally,the power supply/voltage setting terminal 15 supplies a start-up voltageto the connecting point of the collector terminal of the NPN bipolartransistor 11 and the collector terminal of the PNP bipolar transistor22 by way of the start-up circuit 42 composed of the resistor 41, andthereby the constant voltage biasing circuit 2 is started.

In FIG. 2, a case will be examined, in which the input power of the highfrequency amplifier 1 increases and generates the base rectified currentof ΔIb, and consequently the constant voltage biasing circuit 2increases the output of the base current Ibrf by ΔIb. When the basecurrent Ibrf increases by ΔIb, the variations of these currents have thefollowing relations.

ΔIb=ΔIedc2+ΔIbdc1

ΔIedc2=(1+β)*ΔIbdc2

ΔIcdc2=β*ΔIbdc2

ΔIcdc1=−β*ΔIbdc1

${\Delta \quad {Iref}} = {\frac{A \cdot {\beta 2}}{{\beta 2} + 2}\Delta \quad {Icdc2}}$

 ΔIbdc2=ΔIref−ΔIcdc1

Accordingly, $\begin{matrix}{{\Delta \quad {Ibdc2}} = \quad {{\Delta \quad {Iref}} - {\Delta \quad {Icdc1}}}} \\{= \quad {{\frac{A \cdot {\beta 2}}{{\beta 2} + 2}\Delta \quad {Icdc2}} + {{\beta \cdot \Delta}\quad {Ibdc1}}}} \\{= \quad {{\frac{A \cdot {\beta 2} \cdot \beta}{{\beta 2} + 2}\Delta \quad {Ibdc2}} + {{\beta \cdot \Delta}\quad {Ibdc1}}}}\end{matrix}$${{( {1 - \frac{A \cdot {\beta 2} \cdot \beta}{{\beta 2} + 2}} ) \cdot \Delta}\quad {Ibdc2}} = {{\beta \cdot \Delta}\quad {Ibdc1}}$

Therefore,${\Delta \quad {Ibdc2}} = {\frac{\beta}{1 - \frac{A \cdot {\beta 2} \cdot \beta}{{\beta 2} + 2}}\Delta \quad {Ibdc1}}$

On the other hand, $\begin{matrix}{{\Delta \quad {Ib}} = \quad {{\Delta \quad {Iedc2}} + {\Delta \quad {Ibdc1}}}} \\{{= \quad {{\Delta \quad {Ibdc1}} + {( {1 + \beta} )*\Delta \quad {Ibdc2}}}}\quad} \\{= \quad {{\Delta \quad {Ibdc1}} + {\frac{\beta \cdot ( {\beta + 1} )}{1 - \frac{A \cdot {\beta 2} \cdot \beta}{{\beta 2} + 2}}\Delta \quad {Ibdc1}}}} \\{= \quad {{\lbrack {1 + \frac{\beta \cdot ( {\beta + 1} )}{1 - \frac{A \cdot {\beta 2} \cdot \beta}{{\beta 2} + 2}}} \rbrack \cdot \Delta}\quad {Ibdc1}}} \\{{\Delta \quad {Ibdc1}} = \quad {\frac{1}{1 + \frac{\beta \cdot ( {\beta + 1} )}{1 - \frac{A \cdot {\beta 2} \cdot \beta}{{\beta 2} + 2}}}\Delta \quad {Ib}}} \\{= \quad {\frac{1 - \frac{A \cdot {\beta 2} \cdot \beta}{{\beta 2} + 2}}{1 - \frac{A \cdot {\beta 2} \cdot \beta}{{\beta 2} + 2} + {\beta \cdot ( {\beta + 1} )}}\Delta \quad {Ib}}} \\{= \quad {\frac{{\beta 2} + 2 - {A \cdot {\beta 2} \cdot \beta}}{{\beta 2} + 2 - {A \cdot {\beta 2} \cdot \beta} + {\beta \cdot ( {\beta + 1} ) \cdot ( {{\beta 2} + 2} )}}\Delta \quad {Ib}}}\end{matrix}$

The voltage drop at this moment of the NPN bipolar transistor 11 thatforms the current mirror, namely the voltage drop ΔVb of the outputvoltage Vb is given as follows.${\Delta \quad {Vb}} = {\frac{q}{nkT}{\ln ( {1 - \frac{{( {{\beta 2} + 2 - {A \cdot {\beta 2} \cdot \beta}} ) \cdot \Delta}\quad {Ib}}{{Is} \cdot \{ {{\beta 2} + 2 - {A \cdot {\beta 2} \cdot \beta} + {\beta \cdot ( {\beta + 1} ) \cdot ( {{\beta 2} + 2} )}} \} \cdot e^{\frac{qVb}{nkT}}}} )}}$

Where n is the compensation coefficient, k is the Boltzmann's constant,T is the absolute temperature, q the electric charge, and Is thesaturation current.

Therefore, since β2+2<A*β2*β is generally satisfied, ΔVb>0 is deduced.

As described above, in the high frequency amplifying device according tothe embodiment 1 of the present invention, when the high frequency inputsignal Pin increases and generates the base rectified current ΔIb, thebase voltage Vb increases the voltage by ΔVb. As the result, the biasingclass of the high frequency amplifier 1 approaches the A-class when thehigh frequency input signal Pin increases, which makes it possible toincrease the saturation output power and the efficiency.

There is a common practice that interposes a resistor for isolationbetween the base bias terminal 7 of the high frequency amplifier 1 andthe constant voltage biasing circuit 2 in FIG. 2. In that case, when thehigh frequency input signal Pin increases and generates the baserectified current ΔIb, depending on the value of the interposedresistor, it will be possible to increase, regularize, or decrease thebase voltage Vb. Further, an adjustment of the size ratio A of the PNPbipolar transistors 21, 22 that form the current mirror 20 will make itpossible to adjust, i.e., increase, regularize, or decrease the basevoltage Vb, when the high frequency input signal Pin increases andgenerates the base rectified current ΔIb.

However, when the high frequency input signal Pin increases andgenerates the base rectified current ΔIb, and the base voltage Vbincreases by ΔVb, increase of the base voltage Vb will further increasethe base current Ib that flows through the high frequency amplifier 1,and thereby the base voltage Vb will further increase; and thisrepetition will make the circuit operation divergent. Therefore, it willbe important to design the generally interposed isolation resistorbetween the base bias terminal 7 and the constant voltage biasingcircuit 2 and the size ratio A of the PNP bipolar transistors 21, 22that form the current mirror 20 in such a manner that the voltage dropΔVb becomes just zero, or a value infinitely close to zero; and thereby,even when the high frequency input signal Pin increases and generatesthe base rectified current ΔIb, the voltage drop of the base voltage Vbcan be suppressed, and in consequence the high power output and highefficiency can be achieved.

EMBODIMENT 2

FIG. 3 is a circuit diagram illustrating a high frequency amplifyingdevice according to the embodiment 2 of the present invention, and inthe figure, reference numeral 30 signifies a current mirror that usesthe collector current of an NPN bipolar transistor 12 as the referencecurrent, and determines the collector current of an NPN bipolartransistor 11, and 31, 32 signify PMOS transistors (first and secondPMOS transistors) that constitute the current mirror. In the currentmirror, the gates of the PMOS transistors 31, 32 are connected to eachother, the gate and drain terminals of the PMOS transistor 31 arecommonly connected to the collector terminal of the NPN bipolartransistor 12, and the drain terminal of the PMOS transistor 32 isconnected to the base terminal of the NPN bipolar transistor 12.

Further, the resistor (first resistor) 13 is connected between thesource terminal of the PMOS transistor 31 and the power supply/voltage,setting terminal 15, the resistor (second resistor) 14 is connectedbetween the source terminal of the PMOS transistor 32 and the powersupply/voltage setting terminal 15, and a resistor 41 is connectedbetween the drain terminal of the PMOS transistor 32 and the powersupply/voltage setting terminal 15. In addition, a start-up circuit 42composed of the resistor 41.

Next, the operation will be described.

The high frequency signal Pin is input to the high frequency amplifier 1through the high frequency signal input terminal 5, and is output fromthe high frequency signal output terminal 6, after being amplified bythe high frequency amplifier 1. The base voltage Vb and the base currentIbrf are supplied from a constant voltage biasing circuit 2, and thecollector current Icrf and the collector voltage Vc are supplied from acollector bias terminal 8.

In the constant voltage biasing circuit 2, the base voltage Vb and thebase current Ibrf are determined as follows. Herein it is supposed thatthe size of the NPN bipolar transistor 11 that forms the current mirrortogether with the high frequency amplifier 1 is 1, the size of the NPNbipolar transistor 3 of the high frequency amplifier 1 is N, and thesize of the NPN bipolar transistor 12 for the base current compensationis M. Also, it is supposed that these three NPN bipolar transistors 3,11, 12 have the same structure and the same current amplification factorβ. Further, the size ratio of the PMOS transistors 31, 32 that form thecurrent mirror 30 is supposed to be 1:B as shown in FIG. 3. Further, thecontact voltage Vref, the currents Iref, Icdc1, Ibdc1, Icdc2, Iedc2,Ibdc2, Ibrf, Icrf, and the resistor Rref are defined as shown in FIG. 3.

When the power supply voltage Vpc is supplied from the powersupply/voltage setting terminal 15 of the constant voltage biasingcircuit 2, the reference current Iref of the current mirror composed ofthe NPN bipolar transistors 3, 11 is given by the following expression,provided that the voltage across the gate and source of the PMOStransistor 32 is Vgs,

Iref=(Vpc−2*Vb−Vgs)/Rref

With regard to this reference current Iref, the collector current Icrfof the NPN bipolar transistor 3 of the high frequency amplifier 1 isgiven as follows.${Icrf} = {\frac{N}{1 + \frac{1 + N}{\beta \cdot ( {1 + \beta} )}}{Iref}}$

In this case, the base bias voltage Vb of the NPN bipolar transistor 3of the high frequency amplifier 1 is set as follows.

Vb=(Vpc−Iref*Rref−Vgs)/2

The base current Ibrf flowing in this case becomes as follows.

Ibrf=Icrf/β

In this manner, the constant voltage biasing circuit 2 supplies the basevoltage Vb and the base current Ib as the output thereof. Incidentally,the power supply/voltage setting terminal 15 supplies a start-up voltageto the connecting point of the collector terminal of the NPN bipolartransistor 11 and the drain terminal of the PMOS transistor 32 by way ofthe start-up circuit 42 composed of the resistor 41, and thereby theconstant voltage biasing circuit 2 is started.

In FIG. 3, a case will be examined, in which the input power of the highfrequency amplifier 1 increases and generates the base rectified currentof ΔIb, and consequently the constant voltage biasing circuit 2increases the output of the base current Ibrf by ΔIb. When the basecurrent Ibrf increases by ΔIb, the variations of these currents have thefollowing relations.

ΔIb=ΔIedc2+ΔIbdc1

ΔIedc2=(1+β)*ΔIbdc2

ΔIcdc2=β*ΔIbdc2

ΔIcdc1=−β*ΔIbdc1

ΔIref=B*ΔIcdc2

 ΔIbdc2=ΔIref−ΔIcdc1

Therefore,

ΔIbdc2=ΔIref−ΔIcdc1=B*ΔIcdc2+β*ΔIbdc1

(1−B)*ΔIbdc2=β*ΔIbdc1

Accordingly,${\Delta \quad {Ibdc2}} = {\frac{\beta}{1 - B}\Delta \quad {Ibdc1}}$

On the other hand, $\begin{matrix}{{\Delta \quad {Ib}} = \quad {{\Delta \quad {Iedc2}} + {\Delta \quad {Ibdc1}}}} \\{{= \quad {{\Delta \quad {Ibdc1}} + {( {1 + \beta} )*\Delta \quad {Ibdc2}}}}\quad} \\{= \quad {{\Delta \quad {Ibdc1}} + {\frac{\beta \cdot ( {\beta + 1} )}{1 - B}\Delta \quad {Ibdc1}}}} \\{= \quad {{\lbrack {1 + \frac{\beta \cdot ( {\beta + 1} )}{1 - B}} \rbrack \cdot \Delta}\quad {Ibdc1}}}\end{matrix}$ ${Accordingly},\begin{matrix}{{\Delta \quad {Ibdc1}} = \quad {\frac{1}{1 + \frac{\beta \cdot ( {\beta + 1} )}{1 - B}}\Delta \quad {Ib}}} \\{= \quad {\frac{1 - B}{1 - B + {\beta \cdot ( {\beta + 1} )}}\Delta \quad {Ib}}} \\{= \quad {\frac{1 - B}{B^{2} + \beta - B + 2}\Delta \quad {Ib}}}\end{matrix}$

The voltage drop at this moment of the NPN bipolar transistor 11 thatforms the current mirror, namely the voltage drop ΔVb of the outputvoltage Vb is given as follows.${\Delta \quad {Vb}} = {\frac{q}{nkT}{\ln ( {1 - \frac{{( {1 - B} ) \cdot \Delta}\quad {Ib}}{{Is} \cdot ( {\beta^{2} + \beta - B + 2} ) \cdot e^{\frac{qVb}{nkT}}}} )}}$

Therefore, if the relation B>1 is met, ΔVb>0 is deduced; if B=1, ΔVb=0;and if B<1, ΔVb<1.

As described above, in the high frequency amplifying device according tothe embodiment 2 of the present invention, setting the size ratio of thePMOS transistors 31, 32 that form the current mirror 30 into B>1 willmake it possible to raise the base voltage Vb by ΔVb, when the highfrequency input signal Pin increases and generates the base rectifiedcurrent ΔIb. As a result, the biasing class of the high frequencyamplifier 1 approaches the A-class when the high frequency input signalPin increases, which will increase the saturation output power and theefficiency.

Further, setting the size ratio of the PMOS transistors 31, 32 that formthe current mirror 30 into B=1 will make it possible to zero the voltagedrop of the base voltage Vb, when the high frequency input signal Pinincreases and generates the base rectified current ΔIb. As a result, thebiasing class of the high frequency amplifier 1 can be stabilized, whenthe high frequency input signal Pin increases, which will increase thesaturation output power and the efficiency.

In this manner, only a change of the size ratio B of the PMOStransistors 31, 32 that form the current mirror 30 will adjust, i.e.,increase, regularize, or decrease the base voltage Vb, when the highfrequency input signal Pin increases and generates the base rectifiedcurrent ΔIb.

There is a common practice that interposes a resistor for isolationbetween the base bias terminal 7 of the high frequency amplifier 1 andthe constant voltage biasing circuit 2 in FIG. 3. In that case,increasing the size ratio B of the PMOS transistors 31, 32 that form thecurrent mirror 30 for a compensation of the voltage drop by the resistorwill realize all the characteristics mentioned above.

However, when the high frequency input signal Pin increases andgenerates the base rectified current ΔIb, and the base voltage Vbincreases by ΔVb, the increase of the base voltage Vb will furtherincrease the base current Ib that flows through the high frequencyamplifier 1, and thereby the base voltage Vb will further increase; andthis repetition will make the circuit operation divergent.

Therefore, it will be important to design the generally interposedisolation resistor between the base bias terminal 7 and the constantvoltage biasing circuit 2 and the size ratio B of the PMOS transistors31, 32 that form the current mirror 30 in such a manner that the voltagedrop ΔVb becomes just zero, or a value infinitely close to zero; andthereby, even when the high frequency input signal Pin increases andgenerates the base rectified current ΔIb, the voltage drop of the basevoltage Vb can be suppressed, and in consequence the high power outputand high efficiency can be achieved.

Industrial Applicability

As being described above, the high frequency amplifying device accordingto the present invention is able to regularize the base voltage byadjusting the size ratio of the transistors that form the currentmirror, when the high frequency input signal increases and generates thebase rectified current, which is suitable for use in a satellitecommunication, ground microwave communication, and mobile communication,and the like.

What is claimed is:
 1. A high frequency amplifying device comprising: ahigh frequency amplifier that uses a first NPN bipolar transistor as anamplifying element, the collector terminal of said first NPN bipolartransistor being operatively connected to a collector bias terminal; anda constant voltage biasing circuit that supplies a base bias voltage tosaid high frequency amplifier; wherein said constant voltage biasingcircuit includes: a second NPN bipolar transistor that forms a currentmirror together with said first NPN bipolar transistor; a third NPNbipolar transistor that compensates a base current of said currentmirror; a first and second PNP bipolar transistors forming a currentmirror that uses a collector current of said third NPN bipolartransistor as a reference current, and determines a collector current ofsaid second NPN bipolar transistor; and a first and second resistorsthat are operatively connected between the emitter terminals of saidfirst and second PNP bipolar transistors and a power supply/voltagesetting terminal.
 2. A high frequency amplifying device comprising: ahigh frequency amplifier that uses a first NPN bipolar transistor as anamplifying element; and a constant voltage biasing circuit that suppliesa base bias voltage to said high frequency amplifier; wherein saidconstant voltage biasing circuit includes: a second NPN bipolartransistor that forms a current mirror together with said first NPNbipolar transistor; a third NPN bipolar transistor that compensates abase current of said current mirror; a first and second PMOS transistorsforming a current mirror that uses a collector current of said third NPNbipolar transistor as a reference current, and determines a collectorcurrent of said second NPN bipolar transistor; and a first and secondresistors that are interposed between source terminals of said first andsecond PMOS, transistors and a power supply/voltage setting terminal.